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| APU3046 201018073-1/18 data and specifications subject to change without notice. typical application description the APU3046 ic combines a dual synchronous buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications. the dual synchronous con- troller can be configured as 2-independent or 2-phase controller. in 2-phase configuration, the APU3046 provides a programmable current sharing which is ideal when the output power exceeds any single input power budget. APU3046 provides a separate adjustable output by driv- ing a switch as a linear regulator. this device features programmable switching frequency up to 400khz per phase, under-voltage lockout for all input supplies, an external programmable soft-start function as well as out- put under-voltage detection that latches off the device when an output short is detected. dual synchronous controller in 24-pin package with 180 8 out-of-phase operation ldo controller with independent bias supply can be configured as 2-independent or 2-phase pwm controller programmable current sharing in 2-phase configu- ration flexible, same or separate supply operation operation from 4v to 25v input programmable switching frequency up to 400khz soft-start controls all outputs precision reference voltage available 500ma peak output drive capability short circuit protection for all outputs power good output synchronizable with external clock rohs compliant features dual synchronous pwm controller with current sharing circuitry and ldo controller applications technology licensed from international rectifier figure 1 - typical application of APU3046 configured as 2-phase converter with current sharing. dual-phase power supply ddr memory source sink vtt application graphic card hard disk drive power supplies requiring multiple outputs package order information ta (c) device package frequency 0 to 70 APU3046o 24-pin plastic tssop (o) 200-400khz 12v 5v vout2 pgood c1 c2 l1 c6 r2 q5 c18 r10 l4 q4 q1 c5 c7 3.3v u1 vout1 r8 c16 l3 c17 r5 r9 r7 c10 r1 r4 c9 r3 c8 c3 c4 c13 d1 d2 c11 pgnd vcl v out3 ldrv1 hdrv1 fb1 vp2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 fb3 comp1 ss pgood v ref APU3046 l2 c12 q3 c15 r6 q2 c14 sync rt v sen33 vccldo 1n4148 1n4148
2/18 APU3046 electrical specifications unless otherwise specified, these specifications apply over vcc=5v, vch1=vch2=v cl =vccldo=12v and t a =0 to 70c. typical values refer to t a =25c. low duty cycle pulse testing is used which keeps junction and case tem- peratures equal to the ambient temperature. absolute maximum ratings vcc supply voltage .................................................. 25v vccldo, vch1, vch2 and v cl supply voltage ........... 30v (not rated for inductive load) storage temperature range ...................................... -65c to 150c operating junction temperature range ..................... 0c to 125c package information 24-pin plastic tssop (o) parameter sym test condition min typ max units reference voltage section fb voltage fb voltage line regulation uvlo section uvlo threshold - vcc uvlo hysteresis - vcc uvlo threshold - vccldo uvlo hysteresis - vccldo uvlo threshold - vch1 uvlo hysteresis - vch1 uvlo threshold - vch2 uvlo hysteresis - vch2 uvlo threshold - fb uvlo hysteresis - fb uvlo threshold - v sen33 uvlo hysteresis - v sen33 supply current section vcc dynamic supply current vch1 dynamic supply current vch2 dynamic supply current vcc static supply current vch1 static supply current vch2 static supply current vccldo static supply current 5 4/18 APU3046 pin# pin symbol pin description 10,15 11,14 12 13 17 18 19 20 22 23 24 hdrv2, hdrv1 ldrv2, ldrv1 pgnd v cl vccldo v out3 fb3 ss v sen33 pgood gnd output driver for the high side power mosfet. connect a diode, such as bat54 or 1n4148, from these pins to ground for the application when the inductor current goes negative (source/sink), soft-start at no load and for the fast load transient from full load to no load. output driver for the synchronous power mosfet. this pin serves as the separate ground for mosfet?s driver and should be connected to the system?s ground plane. a high frequency capacitor (0.1 to 1 m f) must be connected from vcc, v cl , vch1 and vch2 pins to this pin for noise free operation. supply voltage for the low side output drivers. separate input supply for ldo controller. driver signal for the ldo?s external transistor. ldo?s feedback pin, connected to a resistor divider to set the output voltage of ldo. this pin provides soft-start for the switching regulator. an internal current source charges an external capacitor that is connected from this pin to ground which ramps up the output of the switching regulator, preventing it from overshooting as well as limiting the input current. the converter can be shutdown by pulling this pin below 0.5v. sense the ldo input voltage for uvlo. power good pin. this pin is a collector output that switches low when any of the outputs are outside of the specified under voltage trip point. analog ground for internal reference and control circuitry. connect to pgnd with a short trace. figure 2 - block diagram of the APU3046. bias generator ldrv2 two phase oscillator 1.25v 3v ramp1 fb3 sync 0.5v por por gnd hdrv2 vch2 vccldo ss comp2 1.25v error amp2 pwm comp2 por v out3 25ua 25k 25k reset dom ldrv1 v cl hdrv1 vch1 fb1 comp1 error amp1 pwm comp1 25k 25k reset dom set1 set2 ramp2 64ua max uvlo 4.2v / 4.0v vch2 3.5v / 3.3v vch1 3.5v / 3.3v vsen33 2.5v / 2.3v 4.2v / 4.0v fb2 25k 25k 40ma ldo controller pgnd vccldo vcc rt 1.25v 1.25v v sen33 4 20 21 5 3 6 19 24 18 17 12 11 10 14 15 16 ss>2v vp2 v ref pgood fb3 fb2 fb1 pgood fb2 monitor shut down 10k r s q 22 7 8 1 2 13 9 23 q s r 2v ss block diagram APU3046 5/18 theory of operation introduction the APU3046 is designed for multi-outputs applications. it includes two synchronous buck controllers and a lin- ear regulator controller. the two synchronous controller operates with fixed frequency voltage mode and can be configured as two independent controller or 2-phase con- troller with current sharing. the timing of the ic is pro- vided through an internal oscillator circuit. these are two out of phase oscillators and can be programmed by us- ing an external resistor from 200khz to 400khz per phase. figure 11 shows switching frequency versus ex- ternal resistor. independent mode in this mode the APU3046 provides two independent out- puts with either common or different input voltages. the output voltage of the individual channel is set and con- trolled by the output of the error amplifier, this is the amplified error signal from the sensed output voltage and the reference voltage. this voltage is compared to the ramp signal and generates fixed frequency pulses of vari- able duty-cycle, which drives the two n-channel exter- nal mosfets. current sharing mode in the current sharing mode, the two converter?s outputs tied together and provide one single output (see figure 1). in this mode, one control loop acts as a master and sets the output voltage as a regular voltage mode buck controller and the other control loop acts as a slave and monitors the current information for current sharing. the current sharing is programmable and sets by using two external resistors in output currents? path. the slave's error amplifier, error amplifier 2 (see block diagram) mea- sures the voltage drops across the current sense resis- tors, the differential of these signals is amplified and compared with the ramp signal and generate the fixed frequency pulses of variable duty cycle to match the output currents. out of phase operation the APU3046 drives its two output stages 180 o out of phase. in 2-phase configuration, the two inductor ripple currents cancel each other and result to a reduction of the output current ripple and contribute to a smaller out- put capacitor for the same ripple voltage requirement. in application with single input voltage, the 2-phase con- figuration reduces the input ripple current. this results in much smaller rms current in the input capacitor and reduction of input capacitor. soft-start the APU3046 has a programmable soft start to control the output voltage rise and limit the current surge at the start-up. to ensure correct start-up, the soft-start se- quence initiates when the vcc, vch1, vch2, vccldo and v sen 33 rise above their threshold and generates the power on reset (por) signal. soft-start function oper- ates by sourcing an internal current to charge an exter- nal capacitor to about 3v. initially, the soft-start function clamps the e/a?s output of the pwm converter. as the charging voltage of the external capacitor ramps up, the pwm signals increase from zero to the point the feed- back loop takes control. shutdown the converter can be shutdown by pulling the soft-start pin below 0.5v. this can be easily done by using an external small signal transistor. during shutdown the mosfet drivers and the ldo controller turn off. power good the APU3046 provides a power good signal. this is an open collector output and it is pulled low if the output voltages are not within the specified threshold. this pin can be left floating if not used. short-circuit protection the outputs are protected against the short circuit. the APU3046 protects the circuit for shorted output by sens- ing the output voltages. the APU3046 shuts down the pwm signals and ldo controller, when the output volt- ages drops below the set values. under-voltage lockout the under-voltage lockout circuit assures that the mosfet driver outputs and ldo controller remain in the off state whenever the supply voltages drop below set parameters. normal operation resumes once the supply voltages rise above the set values. frequency synchronization the APU3046 can be synchronized with an external clock signal. the synchronizing pulses must have a minimum pulse width of 100ns. if the sync function is not used, the sync pin can be either connected to ground or be floating. 6/18 APU3046 application information design example: the following example is a typical application for APU3046 in current sharing mode. the schematic is figure 13 on page 15. pwm section output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb1 pin is the inverting input of the error amplifier, which is internally referenced to 1.25v. the divider is ratioed to provide 1.25v at the fb1 pin when the output is at its desired value. the output voltage is defined by using the following equation: when an external resistor divider is connected to the output as shown in figure 3. figure 3 - typical application of the APU3046 for programming the output voltage. equation (1) can be rewritten as: if the high value feedback resistors are used, the input bias current of the fb pin could cause a slight increase in output voltage. the output voltage set point can be more accurate by using precision resistor. soft-start programming the soft-start timing can be programmed by selecting the soft start capacitance value. the start up time of the converter can be calculated by using: where: c ss is the soft-start capacitor ( m f) for a start-up time of 7.5ms, the soft-start capacitor will be 0.1 m f. choose a ceramic capacitor at 0.1 m f. boost supply to drive the high-side switch it is necessary to supply a gate voltage at least 4v greater than the bus voltage. this is achieved by using a charge pump configuration as shown in figure 1. the capacitor is charged up to approximately twice the bus voltage. a capacitor in the range of 0.1 m f to 1 m f is generally adequate for most applications. sense resistor selection these resistors will determine the current sharing between two channels. the relationship between the master and slave output currents is expressed by: for an equal current sharing, r sen1 =r sen1 choose r sen1 =r sen2 =5m v input capacitor selection the input filter capacitor should be based on how much ripple the supply can tolerate on the dc input line. the ripple current generated during the on time of control mosfet should be provided by input capacitor. the rms value of this ripple is expressed by: where: d is the duty cycle, simply d=v out /v in. i rms is the rms value of the input capacitor current. i out is the output current for each channel. for v in1 =5v, i out1 =8a and d1=0.3 results to: i rms1 =3.6a and for v in2 =12v, i out2 =8a and d2=0.125 results to: i rms2 =2.6a t start = 75 3 css (ms) ---(2) fb1 APU3046 v out1 r 5 r 6 for switcher: v in1(master) = 5v v in2(slave) = 12v v out1 = 1.5v i out = 16a d v out = 75mv f s = 200khz for linear regulator: v in3 = 3.3v v out2 = 2.5v i out2 = 2a v out1 = v ref 3 1 + ---(1) r 6 r 5 ( ) r 6 = r 5 3 - 1 v out1 v ref ( ) this will result to: v out1 = 1.5v, v ref = 1.25v, r 5 = 1k, r 6 = 200 v r sen1 3 i master = r sen2 3 i slave ---(3) i rms = i out d 3 (1-d) ---(4) APU3046 7/18 for higher efficiency, a low esr capacitor is recom- mended. for v in1 =5v, choose two poscap from sanyo 6tpb330m (6.3v, 330 m f, 40m v , 3a) for v in2 =12v, choose two 16tpb47m (16v, 47 m f, 70m v , 1.4a). output capacitor selection the criteria to select the output capacitor is normally based on the value of the effective series resistance (esr). in general, the output capacitor must have low enough esr to meet output ripple and load transient requirements, yet have high enough esr to satisfy sta- bility requirements. the esr of the output capacitor is calculated by the following relationship: the sanyo tpc series, poscap capacitor is a good choice. the 6tpc150m 150 m f, 6.3v has an esr 40m v . se- lecting six of these capacitors in parallel, results to an esr of @ 7m v which achieves our low esr goal. the capacitor value must be high enough to absorb the inductor's ripple current. the larger the value of capaci- tor, the lower will be the output ripple voltage. the resulting output ripple current is smaller then each channel ripple current due to the 180 8 phase shift. these currents cancel each other. the cancellation is not the maximum because of the different duty cycle for each channel. inductor selection the inductor is selected based on output power, operat- ing frequency and efficiency requirements. low induc- tor value causes large ripple current, resulting in the smaller size, but poor efficiency and high output noise. generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor ( d i); the optimum point is usually found between 20% and 50% ripple of the output current. where: v in = maximum input voltage v out = output voltage d i = inductor ripple current f s = switching frequency d t = turn on time d = duty cycle for the buck converter, the inductor value for desired operating ripple current can be determined using the fol- lowing relation: for d i 1 =30% of i 1 , we get: l 1 =2.18 m h for d i 2 =30% of i 2 , we get: l 2 =2.7 m h the coilcraft do5022hc series provides a range of in- ductors in different values and low profile for large cur- rents. for l 1 choose: do5022p-222hc (2.2 m h,12a) for l 2 choose: do5022p-332hc (3.3 m h,10a) power mosfet selection the selections criteria to meet power transfer require- ments is based on maximum drain-source voltage (v dss ), gate-source drive voltage (v gs ), maximum output cur- rent, on-resistance r ds(on) and thermal management. the mosfet must have a maximum operating voltage (v dss ) exceeding the maximum input voltage (v in ). the gate drive requirement is almost the same for both mosfets. caution should be taken with devices at very low v gs to prevent undesired turn-on of the complemen- tary mosfet, which results a shoot-through current. the total power dissipation for mosfets includes con- duction and switching losses. for the buck converter the average inductor current is equal to the dc load cur- rent. the conduction loss is defined as: the total conduction loss is defined as: 2 2 p cond (upper switch) = i load 3 r ds(on) 3 d 3 q p cond (lower switch) = i load 3 r ds(on) 3 (1 - d) 3 q q = r ds(on) temperature dependency p con(total) =p con (upper switch) q + p con (lower switch) q esr [ ---(5) d v o d i o where: d v o = output voltage ripple d i o = output current d v o =75mv and d i o =10a, result to esr=7.5m v v in - v out = l 3 ; d t = d 3 ; d = 1 f s v out v in d i d t l = (v in - v out ) 3 ---(6) v out v in 3d i 3 f s 8/18 APU3046 the r ds(on) temperature dependency should be consid- ered for the worst case operation. this is typically given in the mosfet data sheet. ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. choose irf7460 for control mosfet and irf7457 for synchronous mosfet. these devices provide low on- resistance in a compact soic 8-pin package. the mosfets have the following data: the total conduction losses for the master channel is: the total conduction losses for the slave channel is: the control mosfet contributes to the majority of the switching losses in synchronous buck converter. the synchronous mosfet turns on under zero-voltage con- dition, therefore the turn on losses for synchronous mosfet can be neglected. with a linear approxima- tion, the total switching loss can be expressed as: figure 4 - switching time waveforms. from irf7460 data sheet we obtain: these values are taken under a certain condition test. for more detail please refer to the irf7460 and irf7457 data sheets. by using equation (7), we can calculate the switching losses. feedback compensation the control scheme for master and slave channels is based on voltage mode control, but the compensation of these two feedback loops is slightly different. the master channel sets the output voltage and its feed- back loop should take care of double pole introduced by the output filter as a regular voltage mode control loop. the goal is to provide a close loop transfer function with the highest 0db crossing frequency and adequate phase margin. the slave feedback loop acts slightly different and its goal is using the current information for current sharing. the master feedback loop sees the output filter. the out- put lc filter introduces a double pole, -40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 8 (see figure 5). the resonant frequency of the lc filter expressed as follows: figure 5 shows gain and phase of the lc filter. since we already have 180 8 phase shift just from the output filter, the system risks being unstable. figure 5 - gain and phase of lc filter. p sw(master) = 44.8mw p sw(slave) = 107.5mw p con(master) = 0.85w p con(slave) = 0.77w irf7460 v dss = 20v i d = 10a @ 75 8 c r ds(on) = 10m v @ v gs =10v q = 1.8 for 150 8 c (junction temperature) irf7457 v dss = 20v i d = 12a @ 70 8 c r ds(on) = 7.5m v @ v gs =10v q = 1.5 for 150 8 c (junction temperature) where: v ds(off) = drain to source voltage at off time t r = rise time t f = fall time t = switching period i load = load current p sw = 3 3 i load ---(7) v ds(off) 2 t r + t f t f lc(master) = ---(8) 1 2 p lo 3 co irf7460 t r = 6.9ns t f = 4.3ns v ds v gs 10% 90% t d (on) t d (off) t r t f gain f lc 0db phase 0 8 f lc -180 8 frequency frequency -40db/decade APU3046 9/18 the master error amplifier is a differential-input transcon- ductance amplifier. the output is available for dc gain control or ac phase compensation. the e/a can be compensated with or without the use of local feedback. when operated without local feedback the transconductance properties of the e/a become evi- dent and can be used to cancel one of the output filter poles. this will be accomplished with a series rc circuit from comp1 pin to ground as shown in figure 6. the esr zero of the lc filter expressed as follows: figure 6 - compensation network without local feedback and its asymptotic gain plot. the transfer function (ve / v out ) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: the gain is determined by the voltage divider and e/a's transconductance gain. first select the desired zero-crossover frequency (fo): use the following equation to calculate r 4 : where: v in(master) = maximum input voltage v osc = oscillator ramp voltage f o1 = crossover frequency for the master e/a f esr = zero frequency of the output capacitor f lc(master) = resonant frequency of output filter g m = error amplifier transconductor r 5 and r 6 = resistor dividers for output voltage programming this results to: r 4 =29.7k v . choose: r 4 =29.4k v to cancel one of the lc filter poles, place the zero be- fore the lc filter resonant frequency pole: using equations (12) and (14) to calculate c 9 , we get: one more capacitor is sometimes added in parallel with c 9 and r 4 . this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: f o1 > f esr and f o1 [ (1/5 ~ 1/10) 3 f s for: v in(master) = 5v v osc = 1.25v f o1 = 30khz f esr = 25.26khz f lc(master) = 3.57khz r 5 = 1k r 6 = 200 v g m = 600 m mho f p = 2 p 3 r 4 3 c 9 3 c pole c 9 + c pole 1 c 9 = 2003pf choose: c 9 = 2200pf v out v ref r 5 r 6 r 4 c 9 ve e/a1 f z h(s) db frequency gain(db) fb1 comp1 f esr = ---(9) 1 2 p3 esr 3 co |h(s)| = g m 3 3 r 4 ---(11) f z = ---(12) 1 2 p 3 r 4 3 c 9 r 5 r 6 3 r 5 f z @ 75%f lc(master) f z @ 0.75 3 1 2 p l o 3 c o ---(14) for: lo = 2.2 m h co = 900 m f fz = 2.67khz r 4 = 24.9k v r 4 = ---(13) 3 3 3 v osc v in(master) f o1 3 f esr f lc 2 r 5 + r 6 r 5 1 g m h(s) = g m 3 ---(10) ( ) r 5 r 6 + r 5 1 + sr 4 c 9 sc 9 3 10/18 APU3046 the pole sets to one half of switching frequency which results in the capacitor c pole: for a general solution for unconditionally stability for any type of output capacitors, in a wide range of esr values we should implement local feedback with a compensa- tion network. the typically used compensation network for voltage-mode controller is shown in figure 7. figure 7 - compensation network with local feedback and its asymptotic gain plot. in such configuration, the transfer function is given by: the error amplifier gain is independent of the transcon- ductance under the following condition: by replacing z in and z f according to figure 7, the trans- former function can be expressed as: v e 1 - g m z f 1 + g m z in v out = as known, transconductance amplifier has high imped- ance (current source) output, therefore, consider should be taken when loading the e/a output. it may exceed its source/sink output current capability, so that the ampli- fier will not be able to swing its output voltage over the necessary range. the compensation network has three poles and two ze- ros and they are expressed as follows: cross over frequency: the stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. the consideration has been taken to satisfy condition (15) regarding transconduc- tance error amplifier. 1) select the crossover frequency: 2) select r 7 , so that r 7 >> 3) place first zero before lc?s resonant frequency pole. 2 g m fo < f esr and fo [ (1/10 ~ 1/6) 3 f s f z1 @ 75% f lc c 11 = 1 2 p 3 f z1 3 r 7 c pole = @ p 3 r 4 3 f s - 1 c 9 1 1 p 3 r 4 3 f s for f p << f s 2 f p1 = 0 1 2 p3 c 10 3 (r 6 + r 8 ) f z2 = @ 1 2 p3 c 10 3 r 6 f z1 = 1 2 p3 r 7 3 c 11 f p3 = @ 1 2 p3 r 7 3 f p2 = 1 2 p3 r 8 3 c 10 1 2 p3 r 7 3 c 12 c 12 3 c 11 c 12 +c 11 ( ) v out v ref r 5 r 6 r 8 c 10 c 12 c 11 r 7 ve f z 1 f z 2 f p 2 f p 3 e/a1 z f z in frequency gain(db) h(s) db comp1 fb1 g m z f >> 1 and g m z in >>1 ---(15) h(s)= sr 6 (c 12 +c 11 ) 1+sr 7 3 (1+sr 8 c 10 ) 1 (1+sr 7 c 11 ) 3 [1+sc 10 (r 6 +r 8 )] 3 [ ( )] c 12 c 11 c 12 +c 11 where: v in = maximum input voltage v osc = oscillator ramp voltage lo = output inductor co = total output capacitors f o1 = r 7 3 c 10 3 3 ---(16) v in v osc 1 2 p3 lo 3 co APU3046 11/18 f p3 = f s 2 4) place third pole at the half of the switching frequency. c 12 > 50pf if not, change r 7 selection. 5) place r 7 in (16) and calculate c 10 : 6) place second pole at esr zero. f p2 = f esr check if r 8 > if r 8 is too small, increase r 7 and start from step 2. 7) place second zero around the resonant frequency. f z2 = f lc 8) use equation (1) to calculate r 5 : these design rules will give a crossover frequency ap- proximately one-tenth of the switching frequency. the higher the band width, the potentially faster the load tran- sient speed. the gain margin will be large enough to provide high dc-regulation accuracy (typically -5db to - 12db). the phase margin should be greater than 45 8 for overall stability. the slave error amplifier is a differential-input transcon- ductance amplifier as well, the main goal for the slave feed back loop is to control the inductor current to match the masters inductor current as well provides highest bandwidth and adequate phase margin for overall stabil- ity. 1 g m the transfer function of power stage is expressed by: as shown the transfer function is a function of inductor current. the transfer function for the compensation network is given by equation (18), when using a series rc circuit as shown in figure 8: figure 8 - the pi compensation network for slave channel. the loop gain function is: select a zero crossover frequency (f o2 ) one-tenth of the switching frequency: f o2 = 20khz where: v in = input voltage v out = output voltage l 2 = output inductor v osc = oscillator peak voltage c 12 = 1 2 p 3 r 7 3 f p3 r 8 = 1 2 p 3 c10 3 f p2 r 6 = - r 8 1 2 p 3 c10 3 f z2 r 5 = 3 r 6 v ref v out - v ref l 2 l 1 c 2 r 2 r s2 r s1 ve i l2 i l1 fb2 e/a2 comp2 vp2 c 10 [ 3 2 p 3 lo 3 f o 3 co r 7 v osc v in g(s) = = ---(17) i l2 (s) ve(s) v in - v out sl 2 3 v osc d(s) = = ve(s) r s2 3 i l2 (s) 1 + sc 2 r 2 sc 2 ( ) r s1 r s2 ( ) g m 3 3 ---(18) f o2 = f s 10 h(s)=[g(s) 3 d(s) 3 r s2 ] 1+sr 2 c 2 sc 2 ( ) ( ) g m 3 r s1 r s2 ( ) v in -v out sl 2 3 v osc h(s)=r s2 3 3 3 12/18 APU3046 from (18), r 2 can be express as: set the zero of compensator to be half of f lc(slave) , the compensator capacitor, c 2 , can be calculated as: using equations (20) and (21) we get the following val- ues for r 2 and c 2 . ldo section output voltage programming output voltage for ldo is programmed by reference volt- age and external voltage divider. the fb3 pin is the in- verting input of the error amplifier, which is internally ref- erenced to 1.25v. the divider is ratioed to provide 1.25v at the fb3 pin when the output is at its desired value. the output voltage is defined by using the following equa- tion: results to r 7 =1k v c 2 =6606pf; choose: c 2 =6800pf r 2 =16.45k; choose: r 2 =16.5k ldo power mosfet selection the first step in selecting the power mosfet for the linear regulator is to select the maximum r ds(on) based on the input to the dropout voltage and the maximum load current. results to: r ds(on)(max) = 0.4 v note that since the mosfet r ds(on) increases with tem- perature, this number must be divided by ~1.5 in order to find the r ds(on)(max) at room temperature. the irlr2703 has a maximum of 0.065 v r ds(on) at room temperature, which meets our requirements. layout consideration the layout is very important when designing high fre- quency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. start to place the power components, make all the con- nection in the top layer with wide, copper filled areas. the inductor, output capacitor and the mosfet should be close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place input capacitor directly to the drain of the high-side mosfet, to reduce the esr replace the single input capacitor with two par- allel units. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. in multilayer pcb use one layer as power ground plane and have a control cir- cuit ground (analog ground), to which all signals are ref- erenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. r 2 = 3 1 g m 3 r s1 2 p 3 f o2 3 l 2 3 v osc v in(slave) - v out ---(20) r 7 r 10 v out2 = v ref 3 1+ ( ) for: v out2 = 2.5v v ref = 1.25v r 10 = 1k v r ds(on) = v in3 - v out2 i out2 for: v in3 = 3.3v v out2 = 2.5v i out2 = 2a h(fo) = g m 3 r s1 3 r 2 3 =1 ---(19) v in - v out 2 p3 fo 3 l 2 3 v osc f lc(slave) = 1 2 p l 2 3 c out fz = f lc(slave) 2 c 2 = ---(21) 1 2 p 3 r 2 3 fz fb3 APU3046 v out3 r 10 r 7 figure 9 - programming the output voltage for ldo. APU3046 13/18 figure 10 - typical application for APU3046 configured as two independent controllers. typical application figure 11 - switching frequency per phase vs. rt switching frequency vs. rt 190 220 250 280 310 340 370 400 0 100 200 300 400 500 600 rt fs (khz) 12v 5v 2.5v @ 2a pgood c1 33uf l1 c6 47uf r2 1k l4 q1 c5 1uf c7 47uf 3.3v u1 1.8v @ 8a r8 1k c16 2x 150uf l3 c17 2x 150uf r7 442 v c10 0.1uf r1 r4 c9 1500pf r3 c8 2200pf c3 1uf c4 1uf c13 d1 d2 pgnd v cl v out3 ldrv1 hdrv1 fb1 vp2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 fb3 comp1 ss pgood v ref APU3046 c14 2x 47uf sync rt v sen33 vccldo 1uh c11 0.1uf 4.7uh 3.9uh 2.5v @ 8a r9 1k c12 2x 150uf r5 1k fb2 1k 25k 22k irlr2703 q2 irf7460 q3 irf7457 1uf q5 irf7457 q4 irf7457 l2 1uh c2 33uf 1n4148 1n4148 14/18 APU3046 figure 12 - typical application for APU3046 configured for ddr memory application. typical application 12v 5v 1.8v @ 2a pgood c1 33uf l1 c6 47uf r2 1k l3 q1 c5 1uf c7 47uf 3.3v u1 v ddq 2.5v @ 4a r8 1k c16 330uf l2 c17 2x 150uf r7 1k c10 0.1uf r1 r4 c9 5600pf r3 c8 3900pf c3 1uf c4 1uf pgnd v cl v out3 ldrv1 hdrv1 fb1 vp2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 fb3 comp1 ss pgood v ref APU3046 c14 150uf sync rt v sen33 vccldo 1uh 5.6uh 4.7uh v tt 1.25v @ 4a c12 330uf fb2 442 10k 16.2k irlr2703 1/2 of q2 irf7313 c13 1uf 1/2 of q3 irf7313 r9 1k r5 1k v ddq 1/2 of d1 bat54a 1/2 of d1 bat54a 1/2 of q3 irf7313 1/2 of q2 irf7313 APU3046 15/18 demo-board application dual input: 5v and 12v to 1.5v @ 16a figure 13 - demo-board application of APU3046. 12v 5v 2.5v @ 2a pgood c13 47uf 3.3v u1 c29 0.1uf c34 c9 1uf pgnd v cl v out3 ldrv1 hdrv1 fb1 vp2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 fb3 comp1 ss pgood v ref APU3046 q2 irf7457 q1 irf7460 sync rt v sen33 vccldo c7 1uf r6 10 v r7 1k r10 1k c18 47uf r21 16.5k 6.8nf c24 r16 29.4k 2200pf c30 1uf r13 15k q5 irf7457 q4 irf7460 c2 33uf c1 33uf c5 330uf c31 330uf c6 1uf c4 47uf c32 47uf l1 1uh l2 1uh c3 0.1uf d1 bat54s d2 bat54a c23 1uf l4 3.3uh l3 2.2uh r17 r3 5m v 5m v r8 200 r12 1k c10,c11,c12 3x 150uf c15 1uf c19,c20,c21 3x 150uf 1.5v @ 16a c8 1uf r19 4.7 v c26 470pf c14 470pf r5 4.7 v q3 irlr2703 d4 bat54a 16/18 APU3046 ref desig description value qty part# manuf web site (www.) 2 2 1 1 1 2 2 1 1 2 2 2 6 2 1 1 1 2 6 2 4 1 1 2 1 3 2 1 1 q1,q4 q2,q5 q3 u1 d1 d2,d4 l1,l2 l3 l4 c1,c2 c4,c32 c5,c31 c10,11,12, 19,20,21 c3,c29 c9 c24 c34 c14,c26 c6,7,8, 15,23,30 c13,c18 r2,4,15,18 r16 r21 r5,r19 r8 r7,10,12 r3,r17 r13 r6 mosfet mosfet mosfet controller diode diode inductor inductor inductor cap, tantalum cap, poscap cap, poscap cap, poscap cap, ceramic cap, ceramic cap, ceramic cap, ceramic cap, ceramic cap, ceramic cap, tantalum resistor resistor resistor resistor resistor resistor resistor resistor resistor irf7460 irf7457 irlr2703 APU3046 bat54s bat54a or 1n4148 d03316p-102 d05022p-222hc d05022p-332hc ecs-t1cd336r 16tpb47m 6tpb330m 6tpc150m ecj-2vf1e104z ecj-3yb1e105k ecj-2vb1h222k ecj-2vb1h682k ecj-2vc1h471j ecj-2vf1c105z ecs-t1ad476r erj-m1wsf5mou ir ir ir apec ir ir any coilcraft coilcraft coilcraft panasonic sanyo sanyo sanyo panasonic panasonic panasonic panasonic panasonic panasonic panasonic panasonic 20v, 10m v , 12a 20v, 7m v , 15a 30v, 0.045 v , 23a synchronous pwm fast switching fast switching 1 m h, 6.8a 2.2 m h, 12a 3.3 m h, 10a 33 m f, 16v 47 m f, 16v 330 m f, 6.3v 150 m f, 6.3v, 40m v 0.1 m f, y5v, 25v 1 m f, x7r, 25v 2200pf, x7r, 50v 6800pf, x7r, 50v 470pf, x7r, 50v 1 m f, y5v, 16v 47 m f, 10v 2.15 v 29.4k 16.5k 4.7 v 200, 1% 1k, 1% 5m v , 1w, 1% 15k 10 v irf.com coilcraft.com maco.panasonic.co.jp sanyo.com/industrial maco.panasonic.co.jp demo-board application application parts list APU3046 17/18 figure 14 - gate signals vs. inductor currents. ch1: gate signal for control fet(master) (10v/div). ch2: gate signal for control fet(slave) (20v/div). ch3: inductor current for master channel (5a/div). ch4: inductor current for slave channel (5a/div). v master =5v, v slave =12v, i out =10a figure 15 - inductors current matching. ch1: gate signal for sync fet(master) (10v/div). ch2: gate signal for sync fet(slave) (10v/div). ch3: inductor current for master channel (5a/div). ch4: inductor current for slave channel (5a/div). v master =5v, v slave =12v, i out =10a figure 16 - gate signals. ch1: gate signal for control fet(master) (10v/div). ch2: gate signal for sync fet(master) (10v/div). ch3: gate signal for control fet(slave) (20v/div). ch4: gate signal for sync fet(slave) (10v/div). waveforms 18/18 APU3046 figure 17 - start-up @ i out = 10a. figure 18 - transient response @ i out = 0 to 10a. figure 19 - transient response for ldo @ i out = 0 to 2a. v in =5v vss v out 0a 2a 10a 0a waveforms package outline : tssop-24 millimeters symbols min nom max a __ __ 1.20 a1 0.05 __ 0.15 a2 0.08 1.00 1.05 b 0.19 __ 0.30 c 0.09 __ 0.20 d 7.70 7.80 7.90 e __ 6.40 __ e1 4.30 4.40 4.50 e __ 0.65 __ l 0.45 0.60 0.75 __ 1.00 __ __ __ 0.08 0.00 __ 8.00 part marking information & packing : tssop-24 l1 y advanced power electronics corp. u3046o ywwsss package code part number date code (ywwsss) y last digit of the year ww week ssssequence |
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